This invention relates to semiconductor circuits and more particularly to a delay circuit of the type used in clock generators in semiconductor memory devices or the like.
In semiconductor memory devices of the type described in Electronics, Sept. 26, 1978, pp. 109+, or pending application Ser. No. 944822, now U.S. Pat. No. 4,239,993, assigned to Texas Instruments, it is necessary to employ a number of delay circuits in the clock generators to produce clock voltages having a variety of different increments of delay. Usually a stage of amplification is used to create an increment of delay. Here the delay is reliable and tracks well, but the delay increment of one stage of amplification is relatively large, eight to ten nanoseconds for typical device construction. Alternatively, a clock signal can be passed through two separate amplifier stages with one amplifier having more delay than the other, producing two signals differing in time by an increment which can be much less than eight nanoseconds, but this method is critically dependent on device layout and process control to allow the two paths to track.
It is therefore the principal object of this invention to provide an improved delay circuit, particularly one that produces small increments of delay. Another object is to provide a reliable delay circuit which may be used in clock generators for high speed memory devices, or the like.